In this paper, a new lumped element compact Si-based on-chip spiral inductor model is presented for wide-band application. It consists of a new substrate network and underpass oxide leakage component to model the reduction in equivalent series resistance at higher frequencies, taking into account the substrate loss due to eddy current effect. The model accurately estimates the equivalent circuit parameters and inductor behavior over a wide frequency range up to 20GHz. The proposed model has been verified with the measured results of octagonal spiral inductors fabricated on a six-metal BiCMOS7 process. Application of global optimizations genetic algorithm (GA) and particle swarm optimization (PSO) are discussed. PSO is used for the extraction of model parameters that speeds up the convergence and overcomes the sub-optimal solution of conventional optimization algorithm.
Citation:
Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural, "A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design," vlsid, pp.619-624, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006