An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs

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http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.38

19th International Conference on VLSI ...

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	Vivek Garg, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, "An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs," VLSI Design, International Conference on, pp. 507-510, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.

	BibTex	x
	@article{ 10.1109/VLSID.2006.38, author = {Vivek Garg and Vikram Chandrasekhar and M. Sashikanth and V. Kamakoti}, title = {An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2006}, issn = {1063-9667}, pages = {507-510}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.38}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs SN - 1063-9667 SP507 EP510 A1 - Vivek Garg, A1 - Vikram Chandrasekhar, A1 - M. Sashikanth, A1 - V. Kamakoti, PY - 2006 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Vivek Garg, Indian Institute of Technology - Madras

Vikram Chandrasekhar, Indian Institute of Technology - Madras

M. Sashikanth, Indian Institute of Technology - Madras

V. Kamakoti, Indian Institute of Technology - Madras

This paper proposes a function-generation based area-aware Configurable Logic Block (CLB) architecture and an associated packing technique, for SRAM-based FPGAs. The new CLB architecture provides the same logic functionality, but occupies 38% less area, consumes 38.37% less power and requires 50% less configuration-bits per CLB when compared to the standard 4-LUT CLB architecture. The proposed packing technique is timing-driven and is shown to produce designs with almost same routing cost and performance overhead as that produced by the T-VPack algorithm on standard benchmark circuits.

Citation:

Vivek Garg, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, "An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs," vlsid, pp.507-510, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

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