A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency

Hyderabad, India January 03-January 07

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http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.6

19th International Conference on VLSI ...

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	Peter Caputa, Christer Svensson, "A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency," VLSI Design, International Conference on, pp. 117-122, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.

	BibTex	x
	@article{ 10.1109/VLSID.2006.6, author = {Peter Caputa and Christer Svensson}, title = {A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2006}, issn = {1063-9667}, pages = {117-122}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.6}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency SN - 1063-9667 SP117 EP122 A1 - Peter Caputa, A1 - Christer Svensson, PY - 2006 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Peter Caputa, Linköping University

Christer Svensson, Linköping University

We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity-of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18 ?m CMOS process. Transmission-line-style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum. A 22% measured worst-case crosstalk induced delay variation is dominated by inductive coupling.

Citation:

Peter Caputa, Christer Svensson, "A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency," vlsid, pp.117-122, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

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