For the present and future generations of 90nm and more advanced CMOS technologies, technology scaling causes signal lines on the chip to come closer, which results in more coupling capacitances and hence more noise-prone signal lines. The scaling of power supplies decreases the signal- to-noise ratio and thus increases the effect of noise. These factors may cause the chip to fail. Hence, noise analysis becomes critical in the design flow. Noise analysis comprises noise calculation and noise filtering. Crosstalk analysis tools used nowadays typically rely on pessimistic noise filtering approaches and hence report many "false" violations which may not affect the circuit. Noise margin, which is a measure of tolerance to noise, is used in noise filtering. By using less pessimistic noise margin values in noise filtering, false violations, which otherwise cause unnecessary design revisions to be resolved can be eliminated. In this paper, modeling of noise margins with reduced pessimism for standard cells/macros is discussed. Techniques like moving window method and internal node method for standard cells to reduce the characterization time and the time required for channel connected component extraction for complex macros are presented here. Without such reductions, it may not be feasible to do noise characterization. This paper also gives a noise filtering flow and statistical data about net filtering with noise libraries built.