With increase in operating frequency of modern VLSI designs and increase in process variations relative to the nominal process parameters, the chances of multiple input switching have increased. The traditional method of static timing analysis assuming single input switching is no longer adequate enough to capture gate level delays. We propose a new method of systematically modeling gate delays using the high dimensional model representation (HDMR) model. The proposed method models gate delays with respect to the relative signal arrival times (RSAT) of its inputs. The resulting gate delay models can be used for gate-level static timing analysis. The systematic nature of the proposed algorithm allows gate delay characterization with multiple input switching of up to 5 inputs to be reported for the first time. The proposed model is extended to allow the input signal slope and process variations to be taken into account for statistical static timing analysis. Our results show that the proposed HDMR model gives an error between 2.2% to 9.3% compared to SPICE results depending on the number of inputs involved in switching.