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Systems, Nano-technology and SiP
Bangalore, India January 06-January 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.15220th International Conference on VLSI ...
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Rene Penning de Vries, "Systems, Nano-technology and SiP," VLSI Design, International Conference on, pp. 33, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
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@article{ 10.1109/VLSID.2007.152,
author = {Rene Penning de Vries},
title = {Systems, Nano-technology and SiP},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {33},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.152},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Systems, Nano-technology and SiP
SN - 1063-9667
SP
EP
A1 - Rene Penning de Vries,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Rene Penning de Vries, NXP Semiconductors
The on-going trend towards nanoscale technologies creates enormous opportunities for integration of complex functions and features. Many challenges have to be overcome in order to exploit nanoscale technologies for mass production: particularly relevant are CMOS SoC challenges such as low power, design for manufacturability and analog design.
Citation:
Rene Penning de Vries, "Systems, Nano-technology and SiP," vlsid, pp.33, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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