Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix crosstalk violations in the clock tree by making minimal design changes and maintaining skew bounds. We propose a novel approach for making Engineering Change Order (ECO) changes in the clock network to remove crosstalk violations. A two-pronged approach based on wire-translocation and rerouting is presented. Wire translocation, i.e., changing the track for a net to another free track with less crosstalk, eliminates a large percentage of removable violations. A linear time procedure to check if a violation is removable by translocation is developed. Next, an efficient rerouting method based on an incremental loci-finding algorithm is combined with linear time dynamic programming approach to eliminate the remaining crosstalk violations. Simulation results for randomly-generated clock tree of different sizes and benchmark circuits demonstrate the effectiveness of this approach.