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Concurrent Optimization of Technology and Design for Nano CMOS
Bangalore, India January 06-January 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.5120th International Conference on VLSI ...
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Ajith Amerasekera, "Concurrent Optimization of Technology and Design for Nano CMOS," VLSI Design, International Conference on, pp. 27, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
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@article{ 10.1109/VLSID.2007.51,
author = {Ajith Amerasekera},
title = {Concurrent Optimization of Technology and Design for Nano CMOS},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {27},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.51},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Design, International Conference on
TI - Concurrent Optimization of Technology and Design for Nano CMOS
SN - 1063-9667
SP
EP
A1 - Ajith Amerasekera,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Ajith Amerasekera, Texas Instruments
As we move to 45nm and beyond, our ability to manage the need for increased integration together with the drive for higher system performance and lower power presents many challenges to technology and design. It has become no longer possible to consider technology advancement without considering the overall optimization of the transistor and circuit design for full entitlement together with the cost of the chip. This paper looks at the key challenges and technology discontinuities that we face as we move into the nano CMOS regime, and some of the approaches being developed to address them.
Citation:
Ajith Amerasekera, "Concurrent Optimization of Technology and Design for Nano CMOS," vlsid, pp.27, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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