Dynamic circuit techniques offer potential advantages over static CMOS, especially if more complex logic is to be implemented. Therefore, they are extensively used in high performance designs to speed up critical subsystems. However, the speed benefit is traded off for increased power consumption, area overhead, design effort, and reduced noise margins. The continuing process of technology scaling raises further concerns of reliability and limits the wide use of dynamic logic. This paper presents evaluations in terms of area, power dissipation, and propagation delay for several dynamic logic styles as well as for static CMOS in a 90 nm technology. The intention is to assess if dynamic circuit techniques are still an option to boost performance against the background of the issues of nanotechnology. Moreover, issues of reliability and signal integrity, gained from practical experience for different testbenches, and possible solutions are discussed. Finally, an automated design flow for dynamic logic, derived from a standard CMOS flow, is presented.