Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture

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http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.86

20th International Conference on VLSI ...

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	Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov, "Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture," VLSI Design, International Conference on, pp. 805-812, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.

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	@article{ 10.1109/VLSID.2007.86, author = {Edward Flanigan and Rajsekhar Adapa and Hailong Cui and Michael Laisne and Spyros Tragoudas and Tsvetomir Petrov}, title = {Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2007}, issn = {1063-9667}, pages = {805-812}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.86}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture SN - 1063-9667 SP805 EP812 A1 - Edward Flanigan, A1 - Rajsekhar Adapa, A1 - Hailong Cui, A1 - Michael Laisne, A1 - Spyros Tragoudas, A1 - Tsvetomir Petrov, PY - 2007 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Edward Flanigan, Southern Illinois University, Carbondale

Rajsekhar Adapa, Southern Illinois University, Carbondale

Hailong Cui, Qualcomm Incorporated

Michael Laisne, Qualcomm Incorporated

Spyros Tragoudas, Southern Illinois University, Carbondale

Tsvetomir Petrov, Qualcomm Incorporated

In this paper we present a novel function-based test generation technique for path delay faults (PDFs) under the launch-off-capture (LOC) scan architecture. The LOC architecture imposes the condition that the second test pattern must be a functional response of the initial scan test pattern. The proposed function-based LOC methodology incorporates traditional function-based ATPG techniques alongside an implicit framework to efficiently identify testable PDFs under the LOC scan architecture, and avoids the complex backtracking performed by structural techniques which may abort PDF classifications for path intensive designs. The effectiveness and scalability of the proposed method is demonstrated on the path intensive ISCAS 89 benchmarks.

Citation:

Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov, "Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture," vlsid, pp.805-812, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007

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