loading...
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Bangalore, India January 06-January 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.9020th International Conference on VLSI ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir Batterywala, Narendra V Shenoy, Hai Zhou, "Impact of Modern Process Technologies on the Electrical Parameters of Interconnects," VLSI Design, International Conference on, pp. 875-880, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
x
 
@article{ 10.1109/VLSID.2007.90,
author = {Debjit Sinha and Jianfeng Luo and Subramanian Rajagopalan and Shabbir Batterywala and Narendra V Shenoy and Hai Zhou},
title = {Impact of Modern Process Technologies on the Electrical Parameters of Interconnects},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {875-880},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.90},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
SN - 1063-9667
SP875
EP880
A1 - Debjit Sinha,
A1 - Jianfeng Luo,
A1 - Subramanian Rajagopalan,
A1 - Shabbir Batterywala,
A1 - Narendra V Shenoy,
A1 - Hai Zhou,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Debjit Sinha, Northwestern University, Evanston, IL
Jianfeng Luo, ATG, Synopsys Inc., Mountain View, CA 94085, USA
Subramanian Rajagopalan, ATG, Synopsys India Pvt. Ltd., Bangalore, India
Shabbir Batterywala, ATG, Synopsys India Pvt. Ltd., Bangalore, India
Narendra V Shenoy, ATG, Synopsys Inc., Mountain View, CA 94085, USA
Hai Zhou, Northwestern University, Evanston, IL
This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor crosssections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant.
Citation:
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir Batterywala, Narendra V Shenoy, Hai Zhou, "Impact of Modern Process Technologies on the Electrical Parameters of Interconnects," vlsid, pp.875-880, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
Usage of this product signifies your acceptance of the Terms of Use.