Effective TARO Pattern Generation

Palm Springs, California May 01-May 05

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http://doi.ieeecomputersociety.org/10.1109/VTS.2005.43

23rd IEEE VLSI Test Symposium (VTS'05)

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	Intaik Park, Ahmad Al-Yamani, Edward J. McCluskey, "Effective TARO Pattern Generation," VLSI Test Symposium, IEEE, pp. 161-166, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.

	BibTex	x
	@article{ 10.1109/VTS.2005.43, author = {Intaik Park and Ahmad Al-Yamani and Edward J. McCluskey}, title = {Effective TARO Pattern Generation}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2005}, issn = {1093-0167}, pages = {161-166}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.43}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Effective TARO Pattern Generation SN - 1093-0167 SP161 EP166 A1 - Intaik Park, A1 - Ahmad Al-Yamani, A1 - Edward J. McCluskey, PY - 2005 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Intaik Park, Stanford University

Ahmad Al-Yamani, Stanford University and LSI Logic Corporation

Edward J. McCluskey, Stanford University

TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to identify any ATPG tool that can generate TARO test patterns directly. This paper describes a technique to use an existing transition fault ATPG tool to efficiently generate TARO test patterns. This technique was used to generate TARO patterns for the ELF35 test chip. When these patterns were applied to the ELF 35 chips, all of the defective chips were discovered (no test escapes).

Citation:

Intaik Park, Ahmad Al-Yamani, Edward J. McCluskey, "Effective TARO Pattern Generation," vts, pp.161-166, 23rd IEEE VLSI Test Symposium (VTS'05), 2005

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