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Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor
Palm Springs, California May 01-May 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2005.4423rd IEEE VLSI Test Symposium (VTS'05)
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Sreejit Chakravarty, YiShing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W Savage, Rehan Sheikh, Eric N. Tran, Khen Wee, "Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor," VLSI Test Symposium, IEEE, pp. 337-342, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
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@article{ 10.1109/VTS.2005.44,
author = {Sreejit Chakravarty and YiShing Chang and Hiep Hoang and Sridhar Jayaraman and Silvio Picano and Cheryl Prunty and Eric W Savage and Rehan Sheikh and Eric N. Tran and Khen Wee},
title = {Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {337-342},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.44},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor
SN - 1093-0167
SP337
EP342
A1 - Sreejit Chakravarty,
A1 - YiShing Chang,
A1 - Hiep Hoang,
A1 - Sridhar Jayaraman,
A1 - Silvio Picano,
A1 - Cheryl Prunty,
A1 - Eric W Savage,
A1 - Rehan Sheikh,
A1 - Eric N. Tran,
A1 - Khen Wee,
PY - 2005
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Sreejit Chakravarty, Intel Corporation
YiShing Chang, Intel Corporation
Hiep Hoang, Intel Corporation
Sridhar Jayaraman, Intel Corporation
Silvio Picano, Intel Corporation
Cheryl Prunty, Intel Corporation
Eric W Savage, Intel Corporation
Rehan Sheikh, Intel Corporation
Eric N. Tran, Intel Corporation
Khen Wee, Intel Corporation
Silicon evaluation of scan patterns, targeting realistic bridges, for a high performance microprocessor is presented. The practicality of generating realistic bridge patterns is demonstrated. Silicon data, with and without functional fails, and in the presence of n-detect tests are presented. Data points to the value of and efficiency of bridge patterns. Data also shows the advantage of using supplemental bridge patterns when compared with supplemental stuck-at patterns.
Citation:
Sreejit Chakravarty, YiShing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W Savage, Rehan Sheikh, Eric N. Tran, Khen Wee, "Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor," vts, pp.337-342, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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