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Meeting the Test Challenges of the 1 Gbps Parallel RapidIO? Interface with New Automatic Test Equipment Capabilities
Palm Springs, California May 01-May 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2005.5523rd IEEE VLSI Test Symposium (VTS'05)
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Darren Aaberge, Freescale Semiconductor, Inc.
Ken Mockler, Freescale Semiconductor, Inc.
Dieu Van Dinh, Freescale Semiconductor, Inc.
Raoul Belleau, Teradyne, Inc.
Tim Donovan, Teradyne, Inc.
Reid Hewlitt, Teradyne, Inc.
This paper describes an approach to testing the 1Gbps Parallel RapidIO? interface specifications. The unique test requirements for this bus require the application of new test techniques as well as new ATE capabilities. ATE performance attributes important for parallel source-synchronous buses will be identified and presented with methods to measure these attributes.
Index Terms:
RapidIO, Source-Synchronous, ATE, LVDS, Differential, Non-determinism
Citation:
Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt, "Meeting the Test Challenges of the 1 Gbps Parallel RapidIO? Interface with New Automatic Test Equipment Capabilities," vts, pp.75-84, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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