loading...
Transition Tests for High Performance Microprocessors
Palm Springs, California May 01-May 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2005.8723rd IEEE VLSI Test Symposium (VTS'05)
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee, "Transition Tests for High Performance Microprocessors," VLSI Test Symposium, IEEE, pp. 29-34, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/VTS.2005.87,
author = {Yi-Shing Chang and Sreejit Chakravarty and Hiep Hoang and Nick Thorpe and Khen Wee},
title = {Transition Tests for High Performance Microprocessors},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {29-34},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.87},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Transition Tests for High Performance Microprocessors
SN - 1093-0167
SP29
EP34
A1 - Yi-Shing Chang,
A1 - Sreejit Chakravarty,
A1 - Hiep Hoang,
A1 - Nick Thorpe,
A1 - Khen Wee,
PY - 2005
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Yi-Shing Chang, Intel Corporation
Sreejit Chakravarty, Intel Corporation
Hiep Hoang, Intel Corporation
Nick Thorpe, Intel Corporation
Khen Wee, Intel Corporation
The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.
Citation:
Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee, "Transition Tests for High Performance Microprocessors," vts, pp.29-34, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.