Dominance Based Analysis for Large Volume Production Fail Diagnosis

Berkeley, California April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTS.2006.29

24th IEEE VLSI Test Symposium

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	ASCII Text	x
	B. Seshadri, I. Pomeranz, S. Venkataraman, M.E. Amyeen, S.M. Reddy, "Dominance Based Analysis for Large Volume Production Fail Diagnosis," VLSI Test Symposium, IEEE, pp. 392-399, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.29, author = {B. Seshadri and I. Pomeranz and S. Venkataraman and M.E. Amyeen and S.M. Reddy}, title = {Dominance Based Analysis for Large Volume Production Fail Diagnosis}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {392-399}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.29}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Dominance Based Analysis for Large Volume Production Fail Diagnosis SN - 0-7695-2514-8 SP392 EP399 A1 - B. Seshadri, A1 - I. Pomeranz, A1 - S. Venkataraman, A1 - M.E. Amyeen, A1 - S.M. Reddy, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

B. Seshadri, Purdue University

I. Pomeranz, Purdue University

S. Venkataraman, Intel Corporation

M.E. Amyeen, Intel Corporation

S.M. Reddy, University of Iowa

A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9% to 44% average reduction in the fault simulation time for these circuits.

Citation:

B. Seshadri, I. Pomeranz, S. Venkataraman, M.E. Amyeen, S.M. Reddy, "Dominance Based Analysis for Large Volume Production Fail Diagnosis," vts, pp.392-399, 24th IEEE VLSI Test Symposium, 2006

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