Improving Gate-Level ATPG by Traversing Concurrent EFSMs

Berkeley, California April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTS.2006.39

24th IEEE VLSI Test Symposium

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	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli, "Improving Gate-Level ATPG by Traversing Concurrent EFSMs," VLSI Test Symposium, IEEE, pp. 172-179, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.39, author = {Giuseppe Di Guglielmo and Franco Fummi and Cristina Marconcini and Graziano Pravadelli}, title = {Improving Gate-Level ATPG by Traversing Concurrent EFSMs}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {172-179}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Improving Gate-Level ATPG by Traversing Concurrent EFSMs SN - 0-7695-2514-8 SP172 EP179 A1 - Giuseppe Di Guglielmo, A1 - Franco Fummi, A1 - Cristina Marconcini, A1 - Graziano Pravadelli, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Giuseppe Di Guglielmo, Universita di Verona, Italy

Franco Fummi, Universita di Verona, Italy

Cristina Marconcini, Universita di Verona, Italy

Graziano Pravadelli, Universita di Verona, Italy

The paper describes an high-level pseudo-deterministic ATPG that explores the DUT state space by exploiting an easy-totraverse extended FSM model. Testing of hard-to-detect faults is thus improved. Generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.

Citation:

Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli, "Improving Gate-Level ATPG by Traversing Concurrent EFSMs," vts, pp.172-179, 24th IEEE VLSI Test Symposium, 2006

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