Interconnect Testing for Networks on Chips

Berkeley, California April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTS.2006.41

24th IEEE VLSI Test Symposium

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	ASCII Text	x
	Khadija Stewart, Spyros Tragoudas, "Interconnect Testing for Networks on Chips," VLSI Test Symposium, IEEE, pp. 100-107, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.41, author = {Khadija Stewart and Spyros Tragoudas}, title = {Interconnect Testing for Networks on Chips}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {100-107}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.41}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Interconnect Testing for Networks on Chips SN - 0-7695-2514-8 SP100 EP107 A1 - Khadija Stewart, A1 - Spyros Tragoudas, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Khadija Stewart, Southern Illinois University

Spyros Tragoudas, Southern Illinois University

A scheme to functionally test the networking infrastructure of a system within a network on chip is presented. A fault model and a test pattern generation and application algorithm that relies on a network simulator are presented. Experimental results demonstrate the impact of the presented algorithm.

Citation:

Khadija Stewart, Spyros Tragoudas, "Interconnect Testing for Networks on Chips," vts, pp.100-107, 24th IEEE VLSI Test Symposium, 2006

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