RF Front-end System Gain and Linearity Built-in Test

Berkeley, California April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTS.2006.59

24th IEEE VLSI Test Symposium

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	Qi Wang, Mani Soma, "RF Front-end System Gain and Linearity Built-in Test," VLSI Test Symposium, IEEE, pp. 228-233, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.59, author = {Qi Wang and Mani Soma}, title = {RF Front-end System Gain and Linearity Built-in Test}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {228-233}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.59}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - RF Front-end System Gain and Linearity Built-in Test SN - 0-7695-2514-8 SP228 EP233 A1 - Qi Wang, A1 - Mani Soma, PY - 2006 KW - RF test KW - built-in test KW - CMOS RF amplitude detector KW - gfain measurement KW - linearity measurement VL - 0 JA - VLSI Test Symposium, IEEE ER -

Qi Wang, University of Washington

Mani Soma, University of Washington

This work addresses the concurrent on-chip measurement of the gain, the input 1-dB compression point (ICP1-dB), and the input-referred third-order interference point (IIP3) of individual RF building blocks in RF front-end systems, using introduced high speed CMOS RF on-chip amplitude detectors, which work up to 20 GHz with high accuracy, small area, and low power consumption.

Index Terms:

RF test, built-in test, CMOS RF amplitude detector, gfain measurement, linearity measurement

Citation:

Qi Wang, Mani Soma, "RF Front-end System Gain and Linearity Built-in Test," vts, pp.228-233, 24th IEEE VLSI Test Symposium, 2006

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