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Inconsistent Fail due to Limited Tester Timing Accuracy
April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2008.2326th IEEE VLSI Test Symposium (vts 2008)
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Delay testing is a technique to determine if a chip will function correctly at a specified frequency. If a chip passes delay tests, it will presumably function at the specified frequency in the field. This paper presents experimental results that show how chips can pass very thorough delay tests and still fail in the field. It is shown that some chips sometimes pass and sometimes fail when the same delay test is applied multiple times under the same test conditions. These chips are called inconsistent fails. This paper shows how tester timing edge placement accuracy can cause inconsistent fails and suggests the minimum requirements for guardbands that avoid the inconsistent test results.
Index Terms:
delay test, inconsistent fail, inconsistency, tester timing accuracy, tester EPA
Citation:
Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey, "Inconsistent Fail due to Limited Tester Timing Accuracy," vts, pp.47-52, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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