Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric CMOS technologies, the oxide thickness is reduced below a few tens of ? causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open defects. Floating lines can not be considered electrically isolated anymore and are subjected to transient evolutions until arriving at a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of the gate tunnelling leakage is expected to increase for future technologies. The analysis of full opens affecting basic CMOS gates is presented and their defective behaviour characterized. The prediction of the defective logic response of such basic gates is presented for nanometric technologies based on Predictive Technology Models. The final steady state is found to be independent on the initial state of the floating node. Experimental evidence of this behaviour is presented for an industrial chip of 0.18?m technology.