Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring these chips operate at the specified frequency. However, current industrially used X-filling (random-fill or compression) schemes tend to generate transition delay fault patterns with switching activity much higher than what would be seen during functional mode operation of the chip, potentially causing failures that would not occur in the field. In this paper, we present a low switching transition delay fault pattern generation flow. The flow short-lists patterns based on high switching activity, which is determined by the fault lists of each pattern. Once those patterns with high switching are filtered, they will be replaced by low-switching patterns to recover any lost fault coverage. The proposed pattern generation flow works well with commercial tools and can easily be integrated into an industrial flow.