As CMOS scaling continues to decrease and new technologies emerge, feature sizes approach molecular sizes. Due to high defect rates, process variations and quantum effects, manufacturing yields have decreased. To increase the effective yield, error-tolerance, which allows for some defective chips to be employed in systems that can tolerate errors, has been proposed. To support error-tolerance, the acceptability of defective chips must be quantified according to certain measures. A new measure is proposed in this paper, namely significance-based error-rate (SBER). SBER combines two previously studied error-tolerance measures, namely error-significance and error-rate. In this paper we introduce three different ways to quantify the SBER value(s) of a defective chip using built-in self-test (BIST). These techniques cover the following scenarios: (1) multiple copies of a target circuit where at least one copy is non-defective; (2) multiple copies of a target circuit where none are defect free; and (3) single copy of a defective target circuit. For each scenario, the statistical characteristics of the estimation of the SBER value are discussed.